The present invention is generally drawn to a switched mode inductive circuit.
FIG. 1 illustrates a conventional switched mode inductive DCDC converter 100.
As shown in the figure, switched mode inductive DCDC converter 100 includes an input node 102, an inductor 104, a controlling component 106, a power stage 108, a capacitor 110 and an output node 112. Controlling component 106 includes a driving component 114, a driving component 116 and a controller 118. Driving component 114 includes a switch 120 and a switch 122. Driving component 116 includes a switch 124 and a switch 126. Power stage 108 includes a switch 128 and a switch 130. Also shown in switched mode inductive DCDC converter 100, are parasitic inductances 132, 134 and 136.
In the example switched mode inductive DCDC converter 100, switch 120 is a p-channel field effect transistor (p-FET), switch 122 is an n-channel field effect transistor (n-FET), switch 124 is a p-FET, switch 126 is an n-FET, switch 128 is a p-FET and switch 130 is an n-FET.
Inductor 104 is disposed between input node 102 and power stage 108. P-FET 128 is disposed between inductor 104 and output node 112. N-FET 130 is disposed between inductor 104 and ground. Inductor 104, n-FET 130 and p-FET 128 are connected at a node 158. Capacitor 110 is disposed between output node 112 and ground. P-FET 120 and n-FET 122 are disposed between input node 102 and ground, wherein the source of p-FET 120 is connect to input node 102 and wherein the source of n-FET 122 is connected to ground. The drain of p-FET 120 and the drain of n-FET 122 are connected to the gate of n-FET 130 of power stage 108 via a line 138. The gate of p-FET 120 and the gate of n-FET 122 are connected to controller 118 via a line 140. P-FET 124 and n-FET 126 are disposed between input node 102 and ground, wherein the source of p-FET 124 is connect to input node 102 and wherein the source of n-FET 126 is connected to ground. The drain of p-FET 124 and the drain of n-FET 126 are connected to the gate of p-FET 128 of power stage 108 via a line 142. The gate of p-FET 124 and the gate of n-FET 126 are connected to controller 118 via a line 144.
Input node 102 is operable to receive an input voltage, Vin. Inductor 104 is operable to output a first voltage, V1, in a first state and a second voltage, V2, in a second state.
Controlling component 106 is operable to control power stage 108. In particular, controller 118 is operable to control driving component 114 via a control signal 146 on line 140, and is further operable to control driving component 116 via a control signal 148 on line 144. Control signal 146 alternately actuates p-FET 120 and n-FET 122, which in turn provides a bias signal 150 to control n-FET 130 of power stage 108 via line 138. Similarly, control signal 148 alternately actuates p-FET 124 and n-FET 126, which in turn provides a bias signal 152 to control p-FET 128 of power static 108 via line 142.
Power stage 108 operates in a first mode, wherein a current path indicated by arrow 154 travels through inductor 104, through n-FET 130 and to ground. Power stage 108 operates in a second mode, wherein a current path indicated by arrow 156 travels through inductor 104, through p-FET 128 and to output node 112.
Capacitor 110 acts as a low pass filter.
In operation, for purposes of discussion, let conventional switched mode inductive DCDC converter 100 be operating in a first mode, wherein current travels along current path 154. In this mode, controlling component 106 first control power stage 108 such that p-FET 128 is OFF and n-FET 130 is ON. In this case, input node 102 receives Vin, which creates a current along current path 154, through inductor 104, through n-FET 130, through parasitic inductor 136 and finally to ground.
Now, let conventional switched mode inductive DCDC converter 100 switch from the first mode to the second mode, wherein during the switch, there is no current path. While switching between modes, controlling component 106 controls power stage 108 such that, while p-FET 128 remains OFF, n-FET 130 is turned OFF. There should be some time with which p-FET 128 and n-FET 130 are both OFF, to avoid the situation where both switches may be ON, which would short output node 112 to ground.
Then, let controlling component 106 control power stage 108 such that p-FET 128 is turned ON and n-FET 130 remains OFF. In this case, input node 102 receives Vin, which creates a current along current path 156, through inductor 104, through p-FET 128, through parasitic inductor 132 and finally to output node 112.
Conventional switched mode inductive DCDC converter 100 may continue to switch back and forth between the two modes as discussed above, wherein there is a period during the switching when both of p-FET 128 and n-FET 130 are OFF.
At any switching event, the current through inductor 104 needs to change from current path 154 to current path 156, or vice versa. This produces switching loses and therefore reduces the efficiency of the voltage conversion from Vin to Vo. As such, it would be beneficial to switch as quickly as possible. The problem with quickly switching modes is that there are parasitic inductances coming, from bonds wires, PCB and passive components, for example as shown as parasitic inductances 132, 134 and 136. The parasitic inductances do not allow the current to quickly change from current path 154 to current path 156, or vice versa, in zero time. When the dI/dt in the parasitic components reaches high levels that are too high, the parasitic inductors cause voltage ringing. Further, the parasitic components may cause a voltage build up at the drain of one of p-FET 128 or n-FET 130 that could destroy these components. This voltage ringing and voltage build up will now be further described with additional reference to FIGS. 2-4.
FIG. 2 illustrates the voltage at node 158, between the n-FET 130 and p-FET 128, when conventional switched mode inductive DCDC converter 100 switches modes.
The figure includes a graph 200 and a graph 202. Graph 200 includes a y-axis 204, an x-axis 206, a pulse 208 and a pulse 210. Graph 202 includes a y-axis 212, an x-axis 214, a function 216 and a threshold voltage, Vth, indicated by a dotted line 217.
Y-axis 204 has a scale of zero, corresponding to when a FET is OFF, or 1 unit, corresponding to when a FET is ON. X-axis 206 is time and is in units of microseconds. Pulse 208 corresponds to n-FET 130 being ON until a time t1. Line 220 corresponds to n-FET 130 turning OFF, until it is fully OFF at time t2. Therefore, in this case, n-FET 130 takes a period Δt1 to turn OFF. At some time later, p-FET 128 turns ON. Line 221 corresponds to p-FET 128 turning ON, until p-FET 128 is fully ON as shown by line 210.
Y-axis 212 corresponds to a voltage at the drain of n-FET 130 and is measured in volts. X-axis 214 is time and is in units of microseconds. Function 216 corresponds to a voltage at the drain of n-FET 130 as a function of time. Function 216 includes a rising portion 218, a maximum portion 220 and a small ringing portion 222. Dotted line 217 corresponds to Vth, wherein n-FET 130 risks being damaged.
As shown in graph 200, n-FET 130 does not immediately turn OFF. It starts to turn OFF at time t1, and finishes turning OFF at time t2, after Δt1. During that period turning OFF, the current changes from current path 154 to current path 156, creating a parasitic voltage Vpar:Vpar=L*dI/dt,   (1)wherein L s the inductance of parasitic inductors 132 and 136 and dI/dt is the current change. This Vpar builds at the drain of n-FET 130. The voltage reaches a maximum as shown by maximum portion 220. The slope of rising portion 218 is a function of the rate at which n-FET 130 turns OFF, i.e., Δt1. Parasitic capacitances in n-FET 130 resonate with the parasitic inductors within the circuit to generate ringing portion 222. The generation of ringing portion 222 will now be described in greater detail with reference to FIG. 3.
FIG. 3 illustrates parasitic capacitances and inductances associated with n-FET 130 of FIG. 1.
As shown in FIG. 3, a parasitic capacitance 302 is disposed at node 158. Further, in addition to parasitic inductance 136, there exists a parasitic diode 304 in parallel with p-FET 128 not shown), wherein the anode of parasitic diode 304 is disposed toward node 158.
FIG. 3 shows the situation at the moment when n-FET 130 is turned OFF. In this situation, the inductor current, at the moment when n-FET 130 could no longer conduct it, needs to go through parasitic inductance 136 and parasitic diode 304. However an inductor cannot have such a jump in current. This means that physical inductance continues to drive current while it takes a while until parasitic inductance 136 to build up the current. Until the full current can be conducted by parasitic inductance 136, the remaining current is flowing into parasitic capacitance 302, which keeps increasing the voltage at node 158. Parasitic inductance 136 builds up current with a change in the current, i.e.,dI/dt=Vpi/Lpi   (2)wherein Vpi is the voltage across parasitic inductance 136 and wherein Lpi is the inductance of parasitic inductance 136.
Returning to FIG. 2, if maximum portion 220 were to be greater than Vth, then there is a possibility that n-FET 130 may be damaged. This may happen under many circumstances, non-limiting examples of which include operating conventional switched mode inductive DCDC converter 100 at extreme temperatures, and individual component degradation resulting from age or use.
For example, for purposes of discussion, let the period that it takes n-FET 130 to turn OFF increase as a result of operation of conventional switched mode inductive DCDC converter 100 under an extreme temperature. The resulting effect of ringing and voltage build up will be described in greater detail with reference to FIG. 4.
FIG. 4 illustrates the voltage at node 158, between the n-FET 130 and p-FET 128, when conventional switched mode inductive DCDC converter 100, operating in a less than optimum manner, switches modes.
FIG. 4 includes a graph 400 and a graph 402. Graph 400 includes a y-axis 404, an x-axis 406, a pulse 408 and pulse 210. Pulse 208 of FIG. 2 is additionally shown as dotted lines for comparison purposes. Graph 402 includes a y-axis 412, an x-axis 414, a function 416 and threshold voltage, Vth, indicated by dotted line 217. Function 216 of FIG. 2 is additionally shown as a dashed line for comparison purposes.
Y-axis 404 has a scale of zero, corresponding to when a FET is OFF, or 1 unit, corresponding to when a FET is ON. X-axis 406 is time and is in units of microseconds. Pulse 408 corresponds to n-FET 130 being ON until time t1. Line 410 corresponds to n-FET 130 turning OFF, until it is fully OFF at time t3, wherein t3 is less than t2 discussed above with reference to FIG. 2. Therefore, in this case, n-FET 130 takes a period of Δt2 to turn OFF. At some time later, p-FET 128 turns ON.
Y-axis 412 corresponds to a voltage at the drain of n-FET 130 and is measured in volts. X-axis 414 is time and is in units of microseconds. Function 416 corresponds to a voltage at the drain of n-FET 130 as a function of time. Function 416 includes a rising portion 418, a maximum portion 420 and a ringing portion 422.
As shown in graph 400, n-FET 130 does not immediately turn OFF. It starts to turn OFF at time t1, and finishes turning OFF at time t3, after Δt2. During that period of turning OFF, just as discussed above, the current changes from current path 154 to current path 156, creating a parasitic voltage Vpar. In this case, the current change is more drastic than that discussed above with reference to FIG. 2. This is because the period, Δt2, for n-FET 130 to totally turn OFF in this case, is much smaller than the period, Δt1, discussed above with reference to FIG. 2. This can easily be seen by comparing pulse 208 with pulse 408 in FIG. 4.
Just as in the previous example discussed with reference to FIG. 2, in this example Vpar builds at the drain of n-FET 130. The slope of rising portion 418 is a function of the rate at which n-FET 130 turns OFF, i.e., in this case, Δt2. In this case, the slope of rising portion 418 is much greater than the slope of rising portion 218 of function 216. The increased slope translates into a greater voltage build up, which can be seen by comparing maximum portion 420 to maximum portion 220 of function 216. In fact, in this case, maximum portion 420 is greater than Vth, thus risking damage to n-FET 130.
Finally, similar to the situation discussed above with reference to FIG. 2, in this case, parasitic capacitances in n-FET 130 resonate with the parasitic inductors within the circuit to generate ringing portion 422.
What is needed is needed is a switched mode inductive DCDC converter that decreases the likelihood of damage to its components, decreases ringing, and maximizes the overall speed of the circuit